As CMOS technology continues to scale further into the sub-micron region, the width of the gate on metal oxide semiconductor (MOS) transistors is constantly being reduced. MOS transistors gates are formed using a conductive material such as metals, silicides, and doped polycrystalline silicon (polysilicon). For MOS transistor gates formed using doped polysilicon, metal suicides are often formed on the gate structure to reduce the sheet resistance of the gate and to ensure proper electrical contract. The sheet resistance of the gate structure should be as low as possible for proper MOS transistor operation. As the width of the polysilicon gate structure is reduced the sheet resistance of the gate structure rises due in part to the thinner metal silicide regions that are formed on the polysilicon gates using existing fabrication methods. The increased sheet resistance is becoming a major limitation of the MOS transistor performance.
The self-aligned process used to fabricate MOS transistors requires the formation of a sidewall structure prior to the formation of the transistor source and drain regions. Along with the reduction in MOS transistor gate width, the scaling of CMOS technology also requires that the width of the sidewall structures be reduced. The width of the sidewall structure determines how far from the edge of the gate the source and drain regions are formed. During the thermal annealing of the source and drain regions diffusion processes will push the edge of the source and drain regions towards the edge of the transistor gate. Reducing the width of the sidewall structures is therefore limited by the thermal diffusion process that take place during the source drain annealing.
As CMOS technology continues to scale there is therefore an increasing need form methods to reduce the sheet resistance of the MOS transistor gate structure and at the same time reduce the width of the sidewall structure. The instant invention described such a method.